Planetsigma 2013 vlsi and embedded system Intrenships for ece

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planet sigma intrenshipThe goal of PlanetSigma which is located in hyderabad is to provide principal programs that will prepare Engineers for career entry into design, development, and subject-related fields in a learning-centered environment. As part of PlanetSigma placement department, we train Engineers to the core competencies in their perspective languages along with client interviews, resume preparation, ticket resolving etc.

Specialisation:
1. Embedded systems: Duration: 180 days
Eligibility: B.Tech/B.E([ECE/EEE/EIE], MSc.Electronics
2. VLSI: Duration 6 months
Eligibility: B.Tech/B.E([ECE/EEE/EIE], MSc.Electronics
Certificate of Experience:-
Attending this program, students not only have the chance to learn with us, they will be appreciated with a internship certificate stating the Practical Experience & Real Time Experience for a period of six months tenure.

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Download our browser toolbar to get updates of ECE jobs

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ece jobsFirst of all I want to say thanks to all my Visitors, Recently we develop a browser toolbar which shows Updates of Electronics jobs from my websites,so that there is no need to search for my website every time in some where else,its easy for you to visit my website updates which looks like a

browser tool bar

.I hope that my Website is useful for you if you are an electronics student.

don’t miss any electronics opportunity so,DOWNLOAD This toolbar for free.

Download link: http://ecatn.ourtoolbar.com/exe/

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NTPC ET-2013 GATE cutoff marks for interview

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imagesCut off All India Rank (Discipline & Category wise) to short list candidates for Group Discussion and interview.

All India GATE 2013 cutoff ranks for NTPC ET recruitment:

Discipline General OBC SC ST PWD
Electronics 70 217 1008 1441 3507
Electrical 152 547 1700 2483 10591
Mechanical 246 749 2657 5519 11542
Civil 35 118 570 126 2490
Instrumentation 51 134 423 1500 878

 

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Preparation Steps to Success in any competitive Exams

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Competitive exam successNow a days there is a more competition for any competitive exams.Here I am giving some important steps based on my experience to success in any competitive exams related to electronics like BSNL, IES, GATE, BARC, DRDO, ISRO, BHEL, BEL, GAIL, etc……..


Step1: First step is read the notification completely and if they mention any exam date in notification note down the exam date,If they didn’t mention the date then just assume that the exam will be held with in 2 month from the release of notification(now note down the expected/assumed exam date).

Step2: Now next step is to know the syllabus and exam pattern ,search the internet/website of company and take the printout of the syllabus.

Step3: Most important step is to find previous year question papers,Search internet or Buy previous papers books in a market or online.The previous papers are used to give an idea about the exam pattern and to know what type of questions are giving.

Step4: Now check the previous papers questions, are these questions are coming from syllabus or not.If any question is from outside of the syllabus then you just add that topic into syllabus.

Step5: Until Step4 we collect the sources to prepare for the exam.Now according to the exam date and based on your convenience you should prepare a preparation daily plan/Time table.

Step6: According to the Plan/Time table Start your preparation.Before reading any text book first check the previous questions concert to that subject/topic and observe what type of questions are giving, and which areas they covered most,so that its becomes easy to study and give more interest to study.

Step7: Don’t spend more time on reading theory text books,Instead of that practice more objective questions of all previous papers of competitive exams that gives good confidence and shows the way to success..

ONE WHO PRACTICE A LOT WILL DEFINETLY GET SUCCESS.
ALL THE BEST!!!!

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SAIL 2013 Management trainee exam date and admit card

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sailThe date for written test for Management Trainees' examination has been fixed on 14th July, 2013 (Sunday). The admit cards will be available for download from 28th June, 2013 onwards.

For more details: http://sail.shine.com/

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The key to success? Grit from TED video

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Leaving a high-flying job in consulting, Angela Lee Duckworth took a job teaching math to seventh graders in a New York public school. She quickly realized that IQ wasn’t the only thing separating the successful students from those who struggled. Here, she explains her theory of “grit” as a predictor of success.

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BSNL TTA previous electronics model paper download

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bsnl-ttaBSNL is one of the leading telecom circle, and TTA is one of the recruitment for diploma in engineering students,Here I am giving a model TTA electronics objective questions paper based on previous years TTA written exams.I already posted the Syllabus and exam pattern for TTA exam in this website.

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Prasarbharati written exam postponed to 21-Jul-2013

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imagePrasarbharati written exam postponed from 26-May-2013 to 21-Jul-2013,download written exam hall tickets/call letters in www.ssc.nic.in website.This is the good chance to prepare well.

ALL THE BEST!!!!!!!!

Exam timings:

Paper-1 objective is : 10:00 AM to 12:00 Noon (2 hrs)

Paper-2 descriptive is:  2:00 PM to 4:00 PM (2 hrs)

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Institute of Technology (C-DAC) M.Tech admissions

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imageER&DCI-IT is the manpower development and training arm of Centre for Development of Advanced Computing (C-DAC), Thiruvananthapuram, an autonomous institution wholly owned by Department of Information Technology, Government of India. Formerly known as Electronics Research & Development Centre of India (ER&DCI).

Institute of Technology (C-DAC),  Admission Procedure for M.Tech (Electronics) with Specialization in VLSI & Embedded Systems.

Eligibility : B.E/B.Tech degree in Electronics & Communications/ Electronics & Instrumentation/ Electrical & Electronics/ Biomedical Instrumentation of a recognized University, with a minimum of 55% marks for Students with valid Gate Score and 60% marks for students without valid Gate Score, with an aptitude and interest in electronics hardware design

Duration : Four Semester

Selection : Admission is based on GATE Score / DAT Rank .

No. of seats: 18

How to apply:

Eligible candidates may submit the application form at the office on or before 10.05.2013 5.30 pm at The Principal / Administrative Officer, ER&DCI Institute of Technology, C-DAC Campus, Vellayambalam, Thiruvananthapuram – 695 033, Kerala, India.

Click Here For Detail

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