Post name: Memory Modeling Engineer
Responsibilities - Write behavioral models in Verilog/System Verilog for the different flavors of RAMs and ROMs. - Build verification plan and verify the design including behavioral models. - Verify Memory functionality, scan chain using TetraMAX, Formal verification using ESPCV. - Work with internal customers to understand the requirements and support the customers on behavioral models and timing models throughout the design cycle. - Solid understanding of VLSI circuits and Spice simulator is expected. - Drive and build automation with any of the scripting languages like Shell/Perl/TCL to improve the productivity and quality.
- Responsible for driving the verification flow and drive productivity & quality
Skills and Experience - Bachelors/Masters in ECE with 3-5 years of relevant experience. - HDL languages like Verilog, System Verilog. - Spice simulators (Hsim, Finesim) - HDL simulators (Modelsim, VCS, Ncsim) - TetraMAX ATPG verification - ESPCV Formal verification - Scripting using Perl/shell/Tcl Preferred Qualifications - Excellent communication skills and ability to work across multiple teams in multiple locations. - Able to clearly explain ideas and communicate. - Work in a dynamic, team oriented environment.
Qualification: B.Tech / M.Tech
How to apply: Interested candidates should apply online
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