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Friday, 28 October 2016

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Graduate Engineer - in Central Electronics Limited

Qualifications: B.E./B.Tech


Qualification: Full time Bachelor’s Degree or Masters Degree in relevant discipline with not less than 65% marks. Final year/semester students shall also be eligible. However, they would have to obtain at least 65% marks in their engineering degree.

Eligible candidates shall have to appear for Graduate Aptitude Test in Engineering GATE-2017. Based on the GATE-2017 marks and requirement, candidates shall be shortlisted in the Ist stage.


General Instructions

1. Candidates need to appear for GATE-2017 and apply online for the post from 04-01-2017 to 03-02-2017 with the GATE-2017 Registration Number in first phase.

2. In second phase, candidates shall be required to update/upload their GATE Score, GATE Rank & GATE Score Card alongwith final year aggregate marks from 10-06-2017 to 30-06-2017.

3. Requisite fees shall have to be deposited, alongwith the Application. The modalities thereof, shall be intimated subsequently. SC/ST and PH candidates are not required to pay any fees.

4. Upper age limit is relaxable by 5 years for SC/ST, 3 years for OBC (Non Creamy Layer). It is relaxable by 10 years for PwD–General, 13 years for PwD–OBC and 15 years for PwD-SC/ST candidates.

5. Reservation is applicable as per extant government rules.

6. Shortlisted candidates shall be informed displaying a list on website in the month of August, 2017, regarding Date, Time and Venue for Personal Interview.

7. Candidates, if shortlisted for Personal Interview shall be required to bring their original GATE-2017 score card, at the time of Interview.


For more details: http://www.celindia.co.in/drupal7/sites/default/files/GATE-2017-_Advertisement%20-1-_0.pdf

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