Plan your career to get a job in electronics core company

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We are all electronics engineers looking for a job in core company, here I am giving some suggestions to get a core job based on my experience. we know that there are two core sectors one is private and second one is a government sector, you should decide which one we have to choose. If you choose a private sector the preparation will be little bit different than government sector.
  • Most of the government sector companies will recruit talented candidates based on the GATE score, I already discussed and posted the list of companies which are recruiting purely based on GATE score, Now I am discussing about the companies which are recruiting through the written test conducted by them.
  • The written test will consists of Technical(GATE/IES preparation is enough), General English,General aptitude and General awareness. so, you should clear knowledge on both technical and non technical concepts.
  • Now the private sector : In case you have companies visiting your campus , GATE /IES preparation would be enough for you to get through the technical written exams and for non technical: Aptitude,English and basic programming languages.
  • For interviews one can focus on the Projects and Internships. Though preparing all this can help you in the interview it would be advisable that you begin to revise your course subjects from the very start of your final year. This would help you clear your concepts and that is really important.
  • In case the core companies do not visit campus then make sure that you properly utilize your internships and projects and apply in companies that work in similar domains.
  • We gave some core companies list, so you can post your resume through the carrier links provided.
  • The following skills are must for private companies
    1. C Programming - Must
    2. C Language - Basics
    3. Data structures

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Materials used to made a CPU Processor

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Recently, Intel has published a page showing the step-by-step process of how a CPU is made. From sand to its final product, there are many complex steps involved. In fact, it’s absolutely amazing that semiconductor products work at all.
Step 1 – Sand
At about 25% (by mass), silicon is the second most frequent chemical in the earth’s crust (behind oxygen). Sand has a high percentage of Silicon Dioxide (SiO2), which is the base ingredient for semiconductor manufacturing.
Step 2 – Melted Silicon
Silicon is purified in multiple steps to reach the Electronic Grade Silicon used in semiconductors. It ultimately arrives in mono crystal ingots about 12″ in diameter (300mm today, the older ingots were 8″ or 200mm in diameter and smaller — the first wafers in the 1970s were 2″ in diameter, or 50mm).
The purity at this level of refinement is about one part per billion, meaning only one foreign atom per billion silicon atoms. The ingot weighs about 220lbs, and is a 99.9999% pure vertical column of slick glass-looking material.
cpu_step2Step 3 – Ingot Slicing
The ingot is cut with a very thin saw into individual silicon slices (called wafers), each of which are then polished to a flawless mirror-smooth surface. It is upon this totally smooth wafer surface that the tiny copper wires are deposited in the following several steps.
cpu_step3Step 4 – Photo Resist, Exposure
A photo resist liquid is poured onto the wafer while it spins at high speed (similar to materials used in conventional photography). This spinning deposits a thin and even resist layer across the entire surface.
From there, an ultraviolet laser is shone through masks and a lens (which make a focused image 4x smaller than the mask) causing tiny illuminated UV lines on the surface. Everywhere these lines strike the resist, a chemical reaction takes place making those portions soluble.
cpu_step4Step 5 – Washing, etching
The soluble photo resist material is then completely dissolved by a chemical solvent. From there, an etching chemical is used to partially dissolve (or etch) away a tiny quantity of the polished semiconductor material (the substrate). Finally, the remainder of the photo resist material is removed through a similar washing process, revealing the etched surface of the wafer.
cpu_step5Step 6 – Building up layers
In order to create the tiny copper wires which ultimately convey electricity to/from the chip’s various connectors, additional photo resists are added, exposed and washed. Next, a process called ion implantation is used to dope and protect locations where copper ions are deposited from a copper sulfate solution in a process called electroplating.
cpu_step6At various stages during these processes, additional materials are added, exposed, washed / etched and polished. This process is repeated six times for six-layer processes, which is reportedly what Intel uses for their current 45nm high-k, metal gate processes.
The final product looks like a jungle gym, a a host of tiny copper bars which convey electricity. Some of these are connected, some are exactly a specific distance away from other ones. And all of them are used for one purpose: To convey electrons, wielding their electromagnetic effects in a particular way to conduct what we would call “useful work” (such as adding two numbers together at extremely high rates of speed, the very essence of modern day computing).
This multi-layer process is repeated at every single spot on the surface of the entire wafer where chips can be made. This includes even those areas which are partially off the edge of the wafer. Why waste that space? It’s because the early chip makers learned that if they did not fill in these areas with (obviously) wasted semiconductor material, that the chips nearby also had a higher failure rate.
cpu_step8Step 7 – Testing
Once all of the metal layers are built up, and the circuits (transistors) are all created, it’s time for testing. A device with lots of prongs sits down on top of the chip, attaching microscopic leads to the chip’s surface. Each lead completes an electrical connection within the chip, simulating how it would operate in final form once packaged into end-consumer products.
A series of test signals are sent to the chip with whatever the results are being read. This level of testing includes not only traditional computational abilities, but also internal diagnostics along with voltage readings, cascade sequences (does data flow through as it should), etc. And however the chip responds as a result of this testing, is what’s stored in a database assigned specifically for that die.
This process is repeated for every die on the entire wafer’s surface while all dies are still on the surface.
Step 8 – Slicing
A tiny diamond-tipped saw is used to cut the silicon wafer into its various dies. The database derived in Step 7 is used to determine which chips cut from the wafer are kept, and which are discarded. The ones which produced “the right results” in Step 7’s testing are kept, with the rest being thrown away.
cpu_step9Step 9 – Packaging
At this point, all working dies get put into a physical package. It’s important to note that while they’ve had preliminary tested and were found to operate correctly, this doesn’t mean they’re good CPUs.
The physical packaging process involves placing the silicon die onto a green substrate material, to which tiny gold leads are connected to the chip’s pins or ball grid array, which show through the bottom side of the package. On the top of that, a heat spreader is introduced. This appears as the metal package on top of a chip. When finished, the CPU looks like a traditional package end-consumers buy.
Note: The metal heat spreader is a crucial component on modern high-speed semiconductors. In the past, a ceramic top was used with no active cooling. It wasn’t until the 80386 and later time frame, along with some extreme high-speed 8086 and 80286 (100MHz models), that active cooling was required. Prior to that, the chips had so few transistors (the original 8086 had 29K, today’s CPUs have 100s of millions) that they didn’t generate enough heat to require active cooling. To separate themselves, these later ceramic chips were stamped with the warning: “Heatsink required”.
Modern CPUs generate enough heat to melt themselves in a few seconds. Only by having the heat spreader connected to a large heat sink (and fan) can they operate long-term as they do.
cpu_stepfStep 10 – Binning
At this point the package looks like you or I will buy it. Still, there is one more step involved. This final step is called binning.
In this process, the actual characteristics of this particular CPU is measured. Items such as voltage, frequency, performance, heat generation and other internal operational characteristics of its cache, for example, are all measured.
The best chips are generally binned as higher-end parts, being sold as not only the fastest parts with their full caches enabled, but also the low-voltage and ultra low-voltage models. Note: Based on market demand, these highest-end chips can also be sold as lesser chip parts.
Chips which do not perform as well as the best chips are often sold for lower clock speed models, or as a triple- or dual-core (Phenom X3, Phenom X2) instead of their native quad-core. Others may have half their cache disabled (Celeron), etc.
wafer_yieldPerformance and Operational Yields
The process of binning ultimately determines the final yield at given speeds, voltages and thermal characteristics. For example, on a standard wafer only 5% of the chips produced might operate at the highest-end clock rate of 3.2GHz. However, 50% may operate at 2.8GHz.
While this performance yield does not relate to operational yield, it is equally as important to manufacturers as they are constantly looking to determine the reasons why one CPU might operate at 2.8GHz without issue, but not faster, while another operates at 3.2GHz. As the cause of this discrepancy is determined, sometimes the chip’s very design can be updated to increase the performance yield (and operational yields).

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ISRO previous year question papers for electronics and commnications(ECE)


Indian space research organisation is one the center to study about the space.ISRO (Indian Space Research Organization) is to develop space technology and its application to various tasks of national and international interest.
every year they release a notification to recruit a young scientist. So to Get clear the written exam you must start preparation from now onwards.The exam paper will totally objective with negative marking,the syllabus is totally similar to GATE syllabus but some questions will also come from basic computers.

The cutoff for the written exam will changes for every year, But approximately if you get 150 marks then there is a chance of getting call for Interview.

How to prepare to the ISRO written exam:

The exam question will be like a GATE model questions.So be thorough with all the topics and practice all last 10 previous ISRO ,GATE, IES papers.No need to study in depth concepts to clear written exam because there is a less time to study so, practice all previous questions of GATE, IES, ISRO and try yourself to get the solutions to the previous questions. I  think previous question is enough to clear written exam but the chance of Repetition of the questions is very less, they may ask similar models as in previous questions so, practice all the questions clearly.

Mainly concentrate more on weightage subjects like ANALOG CIRCUITS, DIGITAL ELECTRONICS, ELECTROMAGNETIC FIELDS, COMMUNICATIONS,ANTENNA BASICS.  their is a chance of getting more questions from these subjects.

Previous ISRO questions papers with answer in pdf format:

ISRO 2016 paper Download     ANSWER KEY

ISRO 2015 paper Download 

ISRO 2014 paper Download 

ISRO 2013 paper Download

ISRO 2012 paper Download     

ISRO 2011 paper Download 

ISRO 2010 paper Download 

ISRO 2009 paper Download 

ISRO 2008 paper Download 

ISRO 2007 paper Download 

ISRO 2006 paper Download 


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ISRO Electronics Exam pattern and 2017 weightage of marks

ISRO is one of the Space company in india, every year they recruit engineering graduates as a Scientists in one of their centres, ISRO has many centres in india, Here we provide you  exam pattern and weightage analysis for ISRO Electronics exam based on previous year exams.

ISRO Electronics Exam pattern & Selection process:
  • written exam is of objective type.
  • paper consist of 80 questions carries of total 240 Marks and time allotted is 90 mins.
  • Each question carries 3 marks for correct answer (1 Mark is deducted for each wrong answer).
  • Selection is based on written test and performance in interview.
 Following weightage of marks is expected for ISRO Electronics exam.
  • Electromagnetics15 to 20 Questions (45 Marks to 60 Marks)
  • Communications - 15 to 20 Questions (45 Marks to 60 Marks)
  • Electronic Devices – 10 to 12 Questions (30 Marks to 36 Marks)
  • Networks – 7 to 11 Questions (21 Marks to 33 Marks)
  • Digital Circuits & Micro-processor – 6 to 10 Questions (18 Marks to 30 Marks)
  • Signal and Systems – 5 to 7 Questions (15 Marks to 21 Marks)
  • Microwave Engineering – 4 to 6 Questions (12 Marks to 18 Marks)
  • Analog Electronics – 3 to 5 Questions (9 Marks to 15 Marks)
  • Control Systems - 3 to 6 Questions (9 Marks to 18 Marks)


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Know about wearable devices technology

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Wearable devices are miniature electronic devices and their market is expanding at high rate. There are many examples of "wearables¨ available today. For example, smart glasses, ear buds, headphones, smart clothing, smart watches, fitness bands, smart jewellery. Mobile Wearable technologies is the pioneer and worldwide leading innovation and market development platform for technologies worn close to the body, on the body or even in the body. Thus, all types of "wearables" are portable however they are also related to the cloud-based services that take the data from the devices and return analytics and insights to benefit the user.
While designing wearable technologies factors to be considered are as follows:
  •  Power. Power consumption is a critical design requirement and thus a challenge in "wearables". Battery power in "wearables" is expected to last for a significant amount of time.
  •  Connectivity. "Wearables" require connection with other devices via wireless connectivity. Wireless protocols are Wi-Fi, Bluetooth Low Energy, IEEE 802.15.4. Many times wearable devices support more than one wireless protocol.
  • Size. Technology is becoming more and more versatile along with decreasing its size; such technology also attracts the market. Same is the case with wearable devices i.e very powerful functions are to be packed into a very small space. As they need to be compact, a small touchscreen with gesture detection capabilities is carried on wearable electronic. The touchscreen can be capacitive, resistive, surface acoustic wave, and optical imaging.
  •  Aesthetics. While maintaining size and functions, best wearable devices also need to be stylish and fashionable and blend well with other ornaments.
  •  Tolerance. Based on the type of wearable device, tolerance of heat, water and vibrations becomes a necessity. For example, smart watches need to be tolerant to water and same is expected from fitness bands.
Google Glass is one of the most publicized wearable electronic device. Google glass is a pair of glasses to wear that has a mini display screen which can be seen in the corner of vision. There is a touch pad on the side of the glasses which can be used to access information and a camera to capture activities going on in front. It also has a microphone, so voice recognition can be used to type messages or to send commands, same as Apple's Siri or Google's version of Siri, called Google Now.

The wearable market grows more and more as the interaction between watches, phones, glasses, headsets, and clothing increases. So, with more devices in the market each day, developers are needed to build applications for these devices. Wearable devices will change the way applications are designed and developed. For example, Google's Android Wear is an Android platform that will help developers build apps that work on the various wearable devices.
Wearable technologies are used in almost all fields, such as follows:
  • Sports and Fitness. Tracking performance is increasingly important for athletes to get qualified input about vital data during workouts. Wearables devices make such measurements smooth and unobstructive. Some "wearables" widely in use in this category are GPS watches, heart rate monitors and pedometers.
  • Healthcare and wellness. Remote patient monitoring has become possible. Wearable medical devices give patient freedom to move around as they like. 
  •  Security and prevention. Wearable Technologies are used to ensure highest, up-to-date safety and security standards. For example, special lighting technologies for better visibility, home security systems, protective clothing and special gear for extreme sports, rescue teams, workers, or tracking devices for a healthy lifestyle.
  • Gaming and lifestyle. World of gaming is undergoing huge changes, and the "Wearables" are playing a massive role in it.
AUTHOR: Rufyid u Nissa

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Electronics and Communication Engineers-ECE-jobs 2017 (390 vacancies)

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Electronics Engineering Graduates, who pursing 2017 final year or recently 2016 completed engineering degree holders and experienced professionals get your discipline wise suitable Government and private ece core jobs in various companies - latest ece recruitment / ece vacancy details here.

ECE Engineering Graduates recruiting Government of India owned Public Sector Undertakings Companies / private Organizations List: BHEL, BEL, Coal India, HPCL, EIL, BPCL, Mazagon Dock, MECON, NACL, NLC, NMDC, SAIL, NTPC, IOCL, ONGC, Power Grid, Railtel, RITES, UCI,INTEL,CISCO,QUALCOMM etc. Latest Upcoming Graduate Engineering Govt Jobs 2017 listed in the following table. The Total Number of ece Vacancies is Approximate Numbers, but not accurate.

Latest Core jobs for electronics and communication engineers in different companies

here we provide latest job updates for diploma/B.E/ qualified candidates.
Company Post Name-vacancies Last date More details
ISRO Scientist/Engineer -42 07/03/2017 Apply
IIA Engineer Trainee-2 27/02/2017 Apply
Ecil(walkin) Engineer-2 16/02/2017 Apply
Indain navy SSC-10 24/02/2017 Apply
BARC Scientists-10 14/02/2017 Apply
Indian Army SSC-29 vacancy 22/02/2017 Apply
Indian Railway 1.Junior Engineer - 07 vacancies
2. Assistant Loco Pilot- 224 vacancies
10/02/2017 Apply
Centre for Railway Information Systems Junior Software Engineers (JSE)-40
Junior Network engineers-14
08/02/2017 Apply
Vasavi Electronics R&D Engineer-5 vacancy ASAP Apply
Hindustan Petroleum Corporation Limited (HPCL) Engineers-5 vacancy 10/02/2017 Apply

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ISRO Scientist/ Engineer jobs for ECE

Abou Company: Indian Space Research Organization/Department of Space Centres/Units are engaged in Research and Development activities in development of Space Application, Space Science and Technology for the benefit of society at large and for serving the nation by achieving self-reliance and developing capacity to design and build Launch Vehicles and Communication/Remote Sensing Satellites and thereafter launch them. ISRO strives to serve the nation in the areas of television broadcast, Location based services, telecommunication, meteorological application and in management of our natural resources. The Indian space programme continues to pursue successful goals on all fronts in meeting the objective of achieving selfreliance
in space technology and its applications for national development.

Post Name: Scientist/Engineer 'SC’ [Electronics]
No.of Posts: 42 

Last Date: 07-03-2017

Eligibility: BE/B.Tech or equivalent qualification in first class with an aggregate minimum of 65% marks or CGPA 6.84/10 (average of all semesters for which results are available). Candidates applying with qualification of AMIE/Grad IETE should have 65% marks or CGPA 6.84 in Section ‘B’ alone. Candidates who are going to complete the above course in the academic year 2016-17 are also eligible to apply, provided final degree is available by 31/8/2017. The qualification prescribed and the benchmark are only the MINIMUM requirement and fulfilling the same does not automatically make candidates eligible for Written Test.

Application Fee: There will be an Application Fee of ₹100/- (Rupees One Hundred Only) for each application. Candidates may make the payment ‘online’ using Internet Banking/Debit Card or ‘Offline’ by visiting nearest SBI Branch. Candidates after submitting their application can pay application fee immediately or any day before the last date for fee payment i.e. 08.03.2017 (11.59) pm. The last date for submitting online application is 07.03.2017.

How to apply: The application for on-line registration will be hosted in the ISRO web-site between 15.02.2017 and 07.03.2017. Candidates may visit our web-site at to register their applications on-line between 15.02.2017 and 07.03.2017. The candidates registered under National Career Services (NCS) portal and fulfilling the eligibility conditions may visit ISRO website and follow the application procedure as stated. Applications will be received on-line only. Upon registration, applicants will be provided with an on-line Registration Number, which should be carefully preserved for future reference. E-mail ID of the applicant will have to be given in the application compulsorily. The on-line application has to be invariably followed-up with a `No Objection Certificate’ from the employer concerned, by those already in employment under Central/State Government, Public Sector Undertakings or Autonomous Bodies, duly indicating the name and Reg. No. on the reverse

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Apply Online

ISRO Written test Syllabus

ISRO Mock exam 

ISRO Previous papers


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Indian Institute of Astrophysics (IIA) 2017 recruitment

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About Company:  The Indian Institute of Astrophysics (IIA) is an autonomous academic national institution of the Department of Science & Technology, Govt. of India dedicated to research in Astronomy, Astrophysics and Allied Sciences & Technology. The Institute has its main campus in Koramangala, Bengaluru and CREST campus at Hosakote, Bengaluru. It operates field stations at Kavalur & Kodaikanal in Tamil Nadu, Gauribidanur in Karnataka, and Leh/Hanle, Ladakh in Jammu & Kashmir.

India has joined the Thirty Meter Telescope (TMT) project, the next generation astronomical observatory that will be located on Mauna Kea, Hawaii. India’s participation in the TMT Project, led by the Indian Institute of Astrophysics (IIAP, Bengaluru, Inter University Centre for Astronomy and Astrophysics (IUCAA), Pune and Aryabhatta Research Institute for Observational Sciences (ARIES), Nainital is coordinated by the India TMT Coordination Centre (ITCC) hosted at IIA, Bengaluru. The TMT project is an international partnership between California Institute of Technology (CalTech), Universities of California, Canada, Japan, China and India. More details about the project may be obtained from

The Thirty Meter Telescope (TMT) will be the world’s most advanced ground-based observatory that will operate in optical and mid-infrared wavelengths. It will be equipped with the latest innovations in precision control, phased array of mirror segments and laser guide star assisted adaptive optics system. At the heart of the telescope is the segmented mirror, made up of 492 individual hexagonal segments, each 1.44-m in size. Precisely aligned, these segments will work as a single reflective surface of 30-m diameter. India is responsible for providing various critical hardware components and software to the telescope as part of in-kind contribution. Manufacturing of the sub-systems by Indian industry are at various stages.

Online applications are invited from eligible candidates for the following positions to work in the Institute:

Name of the position: ENGINEER TRAINEE
No. of position:No. of position: Two
Age limit : 26 years.
Remuneration : Rs. 20,000/- per month (inclusive of all)
Place of work : Bangalore
Qualification : a)Essential: B.E/B.Tech/M.Sc or equivalent in the field of Electronics and
Telecommunication/Computer Science with a recommended minimum of 60% marks from a recognized University/Institution. Percentage of marks is relaxable if the candidate's technical experience is exceptional.
BCA/MCA with minimum 60% marks from a recognized University/ Institution. Percentage of marks is relaxable if the candidate’s technical experience is exceptional.
b)Desirable: Redhat Certified Engineer (RHCE) certification.
Experience : Candidates having working experience in the field of computer networking, hardware and OS support will get preference.
Scope of work: To support laptop and desktop installation troubleshooting and maintenance with Linux and Windows OS. Installation of required applications on laptops and desktops. LAN troubleshooting and maintenance. Candidate may be required to travel to field stations when required.

The last date for receipt of application is 27.02.2017.
 Important dates to remember
Opening date for on-line registration: 27.01.2017.
Closing date for on-line registration: 27.02.2017.

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ECIL Walk in for Electronics engineer

 ECIL, a Public Sector Enterprise under Department of Atomic Energy is looking for dynamic and result-oriented persons for the following positions on contract basis initially for a period of two years (extendable by one more year depending upon on project requirements) having maintenance experience to work at Kolkata and Guwahati as per the site requirements. 

Qualification & Experience:A First class Engineering Degree in ECE/ CSE/ E&I with minimum 60% marks in aggregate from any recognized Institution/University with 2 (two) years post qualification experience in the field of maintenance of computer hardware, peripherals, LAN & WAN networks, active network equipment’s such as Switches, Modems and Routers, managing and trouble shooting of OS like Windows NT /95 /98 /2000 /XP /2000 server. Certifications like MCP, CCNA shall be preferable.
The walk-in-interviews will be held on 16.02.2017 (Thursday) at ECIL ZONAL OFFICE, 4th FLOOR, APPEJAY HOUSE, 15, PARK STREET, KOLKATA-700016 (WEST BENGAL) Ph.No.033-22172696

HOW TO ATTEND:Eligible candidates may download the application format from our website and attend the interview between 0930 hrs to 1400 hrs. on 16.02.2017 with duly filled in application along with all original certificates in support of date of birth, qualification, experience and caste etc., with one set of photocopies and recent passport size colour photograph at the indicated above.
The selection will be based on interview performance. ECIL reserves the right to cancel/restrict/enlarge/modify the vacancies notified/recruitment process if need so arises, without assigning any reason.
No TA/DA will be paid for attending interview.

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Indian navy 2017 jobs for ECE

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Applications are invited from unmarried Men candidates for grant of Short Service Commission in Executive Branch (General Services/Hydro Cadre) and Technical Branches of the Indian Navy for January 2018 Course at Indian Naval Academy (INA) Ezhimala, Kerala.

Educational Qualifications : Candidates must have completed BE/B. Tech Degree with minimum 60% marks in aggregate from a recognised university in one of the following specified streams:
 Executive (GS) Branch Executive (GS/Hydro Cadre) : BE/B. Tech (Any discipline)

Engineering Branch (General Service) : (i) Marine Mechanical, Aeronautical, (ii) Production, (iii) Metallurgy, (iv) Control, (v) Electrical/Electronics, (vi) Telecommunication, (vii) Computer Science, (viii) Instrumentation, (ix) Instrumentation & Control, (xi) Automotive, (xii) Mechtronics, (xiii) Aerospace & (xiv) BS Engineering

Electrical Branch (General Service) : (i) Electrical (ii) Electronics (iii) Tele Communication (iv) Computer Science (v) Power Engg. (vi) Electronics and Communication (vii) Control System Engg. (viii) Power Electronics (ix) Instrumentation & Control Engg. (x) Electronics & Instrumentation Engg.

Physical Standards : (a) Height& weight: Minimum height Male – 157 cm, Female – 152 cm with correlated weight. Eye Sight : Executive (GS/Hydro) Without Glass : 6/12 With Glass : 6/6 Technical (General Service) Without Glass : 6/24 With Glass : 6/6

 Age Limit : The candidates applying for the above entries must born in 02nd January 1993 to 02nd July 1998 inclusive.

Selection Procedure : (a) The candidates will be issued call up for Services Selection Board (SSB) based on their performance in Degree Course. If a candidate possesses higher qualification with better percentage, his higher qualification will be considered for cut off. Integrated Headquarters, Ministry of Defence (Navy) reserves the right to shortlist applications and to fix cut off percentage. No communication will be entertained on this account. SSB interviews for short listed candidates will be scheduled at Bangalore/ Bhopal/Coimbatore/Visakhapatnam during May 17 to Jul 17.

How to apply: The candidates are to Apply Online (e-application) latest by 24th February,2017.

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BARC 2017 Recruitment of Trainee Scientific Officers

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BARC invites application for the post of recruitment of trainee scientific officers

Last date: 14th February, 2017

Qualifications:Engineers with a B.E./B.Tech./B. Sc (Engg) degree in Mechanical, Chemical, Metallurgical, Electrical, Electronics, Computer, Instrumentation and Civil engineering.

How to apply: interested candidates should apply online before 06-02-2015

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Barc Exam syllaus

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Central Electronics Ltd Recruitment 2017

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Central Electronic Limited(CEL) recruits Graduate Engineers for contract basis through GATE score.

Qualification : Full time Bachelor’s Degree or Masters Degree in relevant discipline with not less than 65% marks. Final year/semester students shall also be eligible. However, they would have to obtain at least 65% marks in their engineering degree. Eligible candidates shall have to appear for Graduate Aptitude Test in Engineering GATE-2017. Based on the GATE-2017 marks and requirement, candidates shall be shortlisted in the 1st stage

How to Apply :
Candidates need to appear for GATE-2017 and apply online for the post from 04-01- 2017 to 03-02-2017.

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