Important objective questions for vlsi core companies

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1. VLSI technology uses ________ to form integrated circuit
a) transistors
b) switches
c) diodes
d) buffers

2. Medium scale integration has
a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates

3. The difficulty in achieving high doping concentration leads to
a) error in concentration
b) error in variation
c) error in doping
d) distrubution error

4. _________ is used to deal with effect of variation
a) chip level technique
b) logic level technique
c) switch level technique
d) system level technique

5. As die size shrinks, the complexity of making the photomasks
a) increases
b) decreases
c) remains the same
d) cannot be determined

6. ______ architecture is used to design VLSI
a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit

7. The design flow of VLSI system is
1. architecture design 2. market requirement 3. logic design 4. HDL coding
a) 2-1-3-4
b) 4-1-3-2
c) 3-2-1-4
d) 1-2-3-4

8. ______ is used in logic design of VLSI
a) LIFO
b) FIFO
c) FILO
d) LILO

9. Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic

10. Physical and electrical specification is given in
a) architectural design
b) logic design
c) system design
d) functional design

11. Which is the high level representation of VLSI design
a) problem statement
b) logic design
c) HDL program
d) functional design

12. Gate minimization technique is used to simplify the logic.
a) true
b) false

13. The condition for linear region is
a) Vgs lesser than Vt
b) Vgs greater than Vt
c) Vds lesser than Vgs
d) Vds greater than Vgs

14. As source drain voltage increases, channel depth
a) increases
b) decreases
c) logarithmically increases
d) exponentially increases

15. Electronics are characterized by
a) low cost
b) low weight and volume
c) reliability
d) all of the mentioned

16.  Speed power product is measured as the product of
a) gate switching delay and gate power dissipation
b) gate switching delay and gate power absorption
c) gate switching delay and net gate power
d) gate power dissipation and absorption

17. nMOS devices are formed in
a) p-type substrate of high doping level
b) n-type substrate of low doping level
c) p-type substrate of moderate doping level
d) n-type substrate of high doping level

18.  Source and drain in nMOS device are isolated by
a) a single diode
b) two diodes
c) three diodes
d) four diodes

19. In depletion mode, source and drain are connected by
a) insulating channel
b) conducing channel
c) Vdd
d) Vss

20. The condition for non saturated region is
a) Vds = Vgs – Vt
b) Vgs lesser than Vt
c) Vds lesser than Vgs – Vt
d) Vds greater than Vgs – Vt

21.  In enhancement mode, device is in _________ condition
a) conducting
b) non conducting
c) partially conducting
d) insulating

22. The condition for non conducting mode is
a) Vds lesser than Vgs
b) Vgs lesser than Vds
c) Vgs = Vds = 0
d) Vgs = Vds = Vs = 0

23.  nMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned

24. MOS transistor structure is
a) symmetrical
b) non symmetrical
c) semi symmetrical
d) pseudo symmetrical

25. pMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned

26. Inversion layer in enhancement mode consists of excess of
a) positive carriers
b) negative carriers
c) both in equal quantity
d) neutral carriers

27. CMOS technology is used in developing
a) microprocessors
b) microcontrollers
c) digital logic circuits
d) all of the mentioned

28.CMOS has
a) high noise margin
b) high packing density
c) high power dissipation
d) high complexity

29. In CMOS fabrication, nMOS and pMOS are integrated in same substrate.
a) true
b) false

30. P-well is created on
a) p subtrate
b) n substrate
c) p & n substrate
d) none of the mentioned

31. Oxidation process is carried out using
a) hydrogen
b) low purity oxygen
c) sulphur
d) nitrogen

32. Photoresist layer is formed using
a) high sensitive polymer
b) light sensitive polymer
c) polysilicon
d) silicon di oxide

33. In CMOS fabrication,the photoresist layer is exposed to
a) visible light
b) ultraviolet light
c) infra red light
d) fluorescent

34. Few parts of photoresist layer is removed by using
a) acidic solution
b) neutral solution
c) pure water
d) diluted water

35. P-well doping concentration and depth will affect the
a) threshold voltage
b) Vss
c) Vdd
d) Vgs

36. Which type of CMOS circuits are good and better?
a) p well
b) n well
c) all of the mentioned
d) none of the mentioned

37. N-well is formed by
a) decomposition
b) diffusion
c) dispersion
d) filtering

38. _______ is sputtered on the whole wafer
a) silicon
b) calcium
c) potassium
d) aluminium

39. Lithography is:
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip

40. Silicon oxide is patterned on a substrate using:
a) Physical lithography
b) Photolithography
c) Chemical lithography
d) Mechanical lithography

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