Important Digital Electronics Logic family objective questions for SAIL and other competitive exams
Important digital electronics logic families objective questions for competitive exams like SAIL BARC,ONGC,Other PSU’S etc,..
b. ECL
c. CMOS
d. MOS
b. TTL
c. ECL
d. CMOS
b. TTL
c. ECL
d. None
b. 15
c. 20
d. 25
b. MOS
c. TTL
d. DTL
b. TTL
c. CMOS
d. CTL
b. CTL
c. ECL
d. CMOS
b. +ve AND
c. +ve NAND
d. None
b. +ve NOR/NAND
c. +ve OR
d. +ve AND
b. CMOS
c. DTL
d. ECL
b. TTL
c. CMOS
d. RTL
b. +ve OR
c. +ve NOR
d. None
b. +ve OR
c. +ve NOR
d. None
b. CMOS
c. TTL
d. ECL
b. TTL
c. DTL
d. ECL
b. TTL
c. DTL
d. ECL
b.unused input that is tied to used inputs.
c. unused input that is tied to the ground.
d. unused input that is not connected.
b. TTL
c. DTL
d. CMOS
b. 0 to 1.8v
c.0 to 2v
d. 0 to 5v
b. Tri state output
c.Totem pole
d.ECL gates
1. Which of the following logic has the fan out of more than 50
a. TTLb. ECL
c. CMOS
d. MOS
2. The most widely used bipolar technology for digital IC’s is
a. DTLb. TTL
c. ECL
d. CMOS
3. Which of the following is the fastest logic family
a. DTLb. TTL
c. ECL
d. None
4. The recommended fan out for TTL is
a. 10b. 15
c. 20
d. 25
5. Highest fan out is present in
a. CMOSb. MOS
c. TTL
d. DTL
6. Which of the following has least propagation delay
a. ECLb. TTL
c. CMOS
d. CTL
7. Which of the following has least power dissipation
a. DTLb. CTL
c. ECL
d. CMOS
8. The Logic type used in ECL is
a. +ve OR/NORb. +ve AND
c. +ve NAND
d. None
9. The Logic type used in CMOS is
a. +ve AND/NANDb. +ve NOR/NAND
c. +ve OR
d. +ve AND
10. Which of the following has more propagation delay
a. MOSb. CMOS
c. DTL
d. ECL
11. Which of the following has highest noise immunity
a. ECLb. TTL
c. CMOS
d. RTL
12. The basic logic gate used in RTL is
a. +ve NANDb. +ve OR
c. +ve NOR
d. None
13. The basic logic gate used in TTL is
a. +ve NANDb. +ve OR
c. +ve NOR
d. None
14. Which of the following is very low speed device
a. MOSb. CMOS
c. TTL
d. ECL
15. Which of the following has low noise margins
a. RTLb. TTL
c. DTL
d. ECL
16.Which of the following logic families has the highest noise margin?
a. CMOSb. TTL
c. DTL
d. ECL
17.A "floating" TTL input may be defined as:
a.unused input that is tied to Vcc through a 1 k resistor.>b.unused input that is tied to used inputs.
c. unused input that is tied to the ground.
d. unused input that is not connected.
18.Which of the logic families listed below allows the highest operating frequency
a. ECLb. TTL
c. DTL
d. CMOS
19.Generally, the voltage measured at an unused TTL input would typically be measured between
a. 1.4 to 1.8vb. 0 to 1.8v
c.0 to 2v
d. 0 to 5v
20. Which TTL logic gate is used for wired ANDing
a. Open collector outputb. Tri state output
c.Totem pole
d.ECL gates
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Thankyou so much for this test paper. I found some free online GATE test papers where aspirants for GATE can practice for free. Check it out: http://thegateacademy.com/gate-free-test/
ReplyDeletereally helpfull. you can also provide a chart of comparison.
ReplyDeleteThis comment has been removed by the author.
ReplyDeleteThis information most useful to me and also your writing skills too good.. In this post most attraction with nice quotes and videos. Thanks and regards: Sarkari Naukri
ReplyDeleteThis page will update all new updates Best Regards Sarkari Result
ReplyDeleteThank u very much to give these information's
ReplyDeleteThanks alot it helps great..
ReplyDeleteIt will help in some exam
ReplyDeleteWell a floating TTL input is considered as logic level high (u can refer any book).
ReplyDelete