Plan your B.tech career to get a job in electronics core company
We are all electronics engineers looking for a job in core company, here I am giving some suggestions to get a core job based on my experience. we know that there are two core sectors one is private and second one is a government sector, you should decide which one we have to choose. If you choose a private sector the preparation will be little bit different than government sector.
- Most of the government sector companies will recruit talented candidates based on the GATE score, I already discussed and posted the list of companies which are recruiting purely based on GATE score, Now I am discussing about the companies which are recruiting through the written test conducted by them.
- The written test will consists of Technical(GATE/IES preparation is enough), General English,General aptitude and General awareness. so, you should clear knowledge on both technical and non technical concepts.
- Now the private sector : In case you have companies visiting your campus , GATE /IES preparation would be enough for you to get through the technical written exams and for non technical: Aptitude,English and basic programming languages.
- For interviews one can focus on the Projects and Internships. Though preparing all this can help you in the interview it would be advisable that you begin to revise your course subjects from the very start of your final year. This would help you clear your concepts and that is really important.
- In case the core companies do not visit campus then make sure that you properly utilize your internships and projects and apply in companies that work in similar domains.
- We gave some core companies list, so you can post your resume through the carrier links provided. The following skills are must for private companies
1. C Programming - Must
2. C Language - Basics
3. Data structures
Ecatn Tags: ece core jobs, after b.tech
Materials used to made a CPU Processor
Recently, Intel has published a page showing the step-by-step process of how a CPU is made. From sand to its final product, there are many complex steps involved. In fact, it’s absolutely amazing that semiconductor products work at all.
At about 25% (by mass), silicon is the second most frequent chemical in the earth’s crust (behind oxygen). Sand has a high percentage of Silicon Dioxide (SiO2), which is the base ingredient for semiconductor manufacturing.
Step 2 – Melted Silicon
Silicon is purified in multiple steps to reach the Electronic Grade Silicon used in semiconductors. It ultimately arrives in mono crystal ingots about 12″ in diameter (300mm today, the older ingots were 8″ or 200mm in diameter and smaller — the first wafers in the 1970s were 2″ in diameter, or 50mm).
The purity at this level of refinement is about one part per billion, meaning only one foreign atom per billion silicon atoms. The ingot weighs about 220lbs, and is a 99.9999% pure vertical column of slick glass-looking material.
Step 3 – Ingot Slicing
The ingot is cut with a very thin saw into individual silicon slices (called wafers), each of which are then polished to a flawless mirror-smooth surface. It is upon this totally smooth wafer surface that the tiny copper wires are deposited in the following several steps.
Step 4 – Photo Resist, Exposure
A photo resist liquid is poured onto the wafer while it spins at high speed (similar to materials used in conventional photography). This spinning deposits a thin and even resist layer across the entire surface.
From there, an ultraviolet laser is shone through masks and a lens (which make a focused image 4x smaller than the mask) causing tiny illuminated UV lines on the surface. Everywhere these lines strike the resist, a chemical reaction takes place making those portions soluble.
Step 5 – Washing, etching
The soluble photo resist material is then completely dissolved by a chemical solvent. From there, an etching chemical is used to partially dissolve (or etch) away a tiny quantity of the polished semiconductor material (the substrate). Finally, the remainder of the photo resist material is removed through a similar washing process, revealing the etched surface of the wafer.
Step 6 – Building up layers
In order to create the tiny copper wires which ultimately convey electricity to/from the chip’s various connectors, additional photo resists are added, exposed and washed. Next, a process called ion implantation is used to dope and protect locations where copper ions are deposited from a copper sulfate solution in a process called electroplating.
At various stages during these processes, additional materials are added, exposed, washed / etched and polished. This process is repeated six times for six-layer processes, which is reportedly what Intel uses for their current 45nm high-k, metal gate processes.
The final product looks like a jungle gym, a a host of tiny copper bars which convey electricity. Some of these are connected, some are exactly a specific distance away from other ones. And all of them are used for one purpose: To convey electrons, wielding their electromagnetic effects in a particular way to conduct what we would call “useful work” (such as adding two numbers together at extremely high rates of speed, the very essence of modern day computing).
This multi-layer process is repeated at every single spot on the surface of the entire wafer where chips can be made. This includes even those areas which are partially off the edge of the wafer. Why waste that space? It’s because the early chip makers learned that if they did not fill in these areas with (obviously) wasted semiconductor material, that the chips nearby also had a higher failure rate.
Step 7 – Testing
Once all of the metal layers are built up, and the circuits (transistors) are all created, it’s time for testing. A device with lots of prongs sits down on top of the chip, attaching microscopic leads to the chip’s surface. Each lead completes an electrical connection within the chip, simulating how it would operate in final form once packaged into end-consumer products.
A series of test signals are sent to the chip with whatever the results are being read. This level of testing includes not only traditional computational abilities, but also internal diagnostics along with voltage readings, cascade sequences (does data flow through as it should), etc. And however the chip responds as a result of this testing, is what’s stored in a database assigned specifically for that die.
This process is repeated for every die on the entire wafer’s surface while all dies are still on the surface.
Step 8 – Slicing
A tiny diamond-tipped saw is used to cut the silicon wafer into its various dies. The database derived in Step 7 is used to determine which chips cut from the wafer are kept, and which are discarded. The ones which produced “the right results” in Step 7’s testing are kept, with the rest being thrown away.
Step 9 – Packaging
At this point, all working dies get put into a physical package. It’s important to note that while they’ve had preliminary tested and were found to operate correctly, this doesn’t mean they’re good CPUs.
The physical packaging process involves placing the silicon die onto a green substrate material, to which tiny gold leads are connected to the chip’s pins or ball grid array, which show through the bottom side of the package. On the top of that, a heat spreader is introduced. This appears as the metal package on top of a chip. When finished, the CPU looks like a traditional package end-consumers buy.
Note: The metal heat spreader is a crucial component on modern high-speed semiconductors. In the past, a ceramic top was used with no active cooling. It wasn’t until the 80386 and later time frame, along with some extreme high-speed 8086 and 80286 (100MHz models), that active cooling was required. Prior to that, the chips had so few transistors (the original 8086 had 29K, today’s CPUs have 100s of millions) that they didn’t generate enough heat to require active cooling. To separate themselves, these later ceramic chips were stamped with the warning: “Heatsink required”.
Modern CPUs generate enough heat to melt themselves in a few seconds. Only by having the heat spreader connected to a large heat sink (and fan) can they operate long-term as they do.
Step 10 – Binning
At this point the package looks like you or I will buy it. Still, there is one more step involved. This final step is called binning.
In this process, the actual characteristics of this particular CPU is measured. Items such as voltage, frequency, performance, heat generation and other internal operational characteristics of its cache, for example, are all measured.
The best chips are generally binned as higher-end parts, being sold as not only the fastest parts with their full caches enabled, but also the low-voltage and ultra low-voltage models. Note: Based on market demand, these highest-end chips can also be sold as lesser chip parts.
Chips which do not perform as well as the best chips are often sold for lower clock speed models, or as a triple- or dual-core (Phenom X3, Phenom X2) instead of their native quad-core. Others may have half their cache disabled (Celeron), etc.
Performance and Operational Yields
The process of binning ultimately determines the final yield at given speeds, voltages and thermal characteristics. For example, on a standard wafer only 5% of the chips produced might operate at the highest-end clock rate of 3.2GHz. However, 50% may operate at 2.8GHz.
While this performance yield does not relate to operational yield, it is equally as important to manufacturers as they are constantly looking to determine the reasons why one CPU might operate at 2.8GHz without issue, but not faster, while another operates at 3.2GHz. As the cause of this discrepancy is determined, sometimes the chip’s very design can be updated to increase the performance yield (and operational yields).
ISRO Electronics Exam pattern and 2017 weightage of marks
ISRO is one of the Space company in india, every year they recruit engineering graduates as a Scientists in one of their centres, ISRO has many centres in india, Here we provide you exam pattern and weightage analysis for ISRO Electronics exam based on previous year exams.
ISRO Electronics Exam pattern & Selection process:
ISRO Electronics Exam pattern & Selection process:
- written exam is of objective type.
- paper consist of 80 questions carries of total 240 Marks and time allotted is 90 mins.
- Each question carries 3 marks for correct answer (1 Mark is deducted for each wrong answer).
- Selection is based on written test and performance in interview.
- Electromagnetics – 15 to 20 Questions (45 Marks to 60 Marks)
- Communications - 15 to 20 Questions (45 Marks to 60 Marks)
- Electronic Devices – 10 to 12 Questions (30 Marks to 36 Marks)
- Networks – 7 to 11 Questions (21 Marks to 33 Marks)
- Digital Circuits & Micro-processor – 6 to 10 Questions (18 Marks to 30 Marks)
- Signal and Systems – 5 to 7 Questions (15 Marks to 21 Marks)
- Microwave Engineering – 4 to 6 Questions (12 Marks to 18 Marks)
- Analog Electronics – 3 to 5 Questions (9 Marks to 15 Marks)
- Control Systems - 3 to 6 Questions (9 Marks to 18 Marks)
Know about wearable devices technology
Wearable devices are miniature electronic devices and their market is expanding at high rate. There are many examples of "wearables¨ available today. For example, smart glasses, ear buds, headphones, smart clothing, smart watches, fitness bands, smart jewellery. Mobile Wearable technologies is the pioneer and worldwide leading innovation and market development platform for technologies worn close to the body, on the body or even in the body. Thus, all types of "wearables" are portable however they are also related to the cloud-based services that take the data from the devices and return analytics and insights to benefit the user.
While designing wearable technologies factors to be considered are as follows:
The wearable market grows more and more as the interaction between watches, phones, glasses, headsets, and clothing increases. So, with more devices in the market each day, developers are needed to build applications for these devices. Wearable devices will change the way applications are designed and developed. For example, Google's Android Wear is an Android platform that will help developers build apps that work on the various wearable devices.
Wearable technologies are used in almost all fields, such as follows:
While designing wearable technologies factors to be considered are as follows:
- Power. Power consumption is a critical design requirement and thus a challenge in "wearables". Battery power in "wearables" is expected to last for a significant amount of time.
- Connectivity. "Wearables" require connection with other devices via wireless connectivity. Wireless protocols are Wi-Fi, Bluetooth Low Energy, IEEE 802.15.4. Many times wearable devices support more than one wireless protocol.
- Size. Technology is becoming more and more versatile along with decreasing its size; such technology also attracts the market. Same is the case with wearable devices i.e very powerful functions are to be packed into a very small space. As they need to be compact, a small touchscreen with gesture detection capabilities is carried on wearable electronic. The touchscreen can be capacitive, resistive, surface acoustic wave, and optical imaging.
- Aesthetics. While maintaining size and functions, best wearable devices also need to be stylish and fashionable and blend well with other ornaments.
- Tolerance. Based on the type of wearable device, tolerance of heat, water and vibrations becomes a necessity. For example, smart watches need to be tolerant to water and same is expected from fitness bands.
The wearable market grows more and more as the interaction between watches, phones, glasses, headsets, and clothing increases. So, with more devices in the market each day, developers are needed to build applications for these devices. Wearable devices will change the way applications are designed and developed. For example, Google's Android Wear is an Android platform that will help developers build apps that work on the various wearable devices.
Wearable technologies are used in almost all fields, such as follows:
- Sports and Fitness. Tracking performance is increasingly important for athletes to get qualified input about vital data during workouts. Wearables devices make such measurements smooth and unobstructive. Some "wearables" widely in use in this category are GPS watches, heart rate monitors and pedometers.
- Healthcare and wellness. Remote patient monitoring has become possible. Wearable medical devices give patient freedom to move around as they like.
- Security and prevention. Wearable Technologies are used to ensure highest, up-to-date safety and security standards. For example, special lighting technologies for better visibility, home security systems, protective clothing and special gear for extreme sports, rescue teams, workers, or tracking devices for a healthy lifestyle.
- Gaming and lifestyle. World of gaming is undergoing huge changes, and the "Wearables" are playing a massive role in it.
Central Electronics Ltd Recruitment 2017
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Central Electronic Limited(CEL) recruits Graduate Engineers for contract basis through GATE score.
Qualification : Full time Bachelor’s Degree or Masters Degree in relevant discipline with not less than 65% marks. Final year/semester students shall also be eligible. However, they would have to obtain at least 65% marks in their engineering degree. Eligible candidates shall have to appear for Graduate Aptitude Test in Engineering GATE-2017. Based on the GATE-2017 marks and requirement, candidates shall be shortlisted in the 1st stage
How to Apply :
Candidates need to appear for GATE-2017 and apply online for the post from 04-01- 2017 to 03-02-2017.
Click here for more details
Qualification : Full time Bachelor’s Degree or Masters Degree in relevant discipline with not less than 65% marks. Final year/semester students shall also be eligible. However, they would have to obtain at least 65% marks in their engineering degree. Eligible candidates shall have to appear for Graduate Aptitude Test in Engineering GATE-2017. Based on the GATE-2017 marks and requirement, candidates shall be shortlisted in the 1st stage
How to Apply :
Candidates need to appear for GATE-2017 and apply online for the post from 04-01- 2017 to 03-02-2017.
Click here for more details
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