ECE core companies interview questions
1. Which among the following is a process
of transforming design entry information of the circuit into a set of logic
equations?
a. Simulation
b. Optimization
c. Synthesis
d. Verification
b. Optimization
c. Synthesis
d. Verification
ANSWER: Synthesis
2. _________ is the fundamental
architecture block or element of a target PLD.
a. System Partitioning
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation
b. Pre-layout Simulation
c. Logic cell
d. Post-layout Simulation
ANSWER: Logic cell
3. In VLSI design, which process
deals with the determination of resistance & capacitance of
interconnections?
a. Floor planning
b. Placement & Routing
c. Testing
d. Extraction
b. Placement & Routing
c. Testing
d. Extraction
ANSWER: Extraction
4. In
Net-list language, the net-list is generated _______synthesizing VHDL code.
a. Before
b. At the time of (during)
c. After
d. None of the above
b. At the time of (during)
c. After
d. None of the above
ANSWER: After
5. In
VHDL, which object/s is/are used to connect entities together for the model
formation?
a. Constant
b. Variable
c. Signal
d. All of the above
b. Variable
c. Signal
d. All of the above
ANSWER: Signal
6. Which
type of simulation mode is used to check the timing performance of a design?
a. Behavioral
b. Switch-level
c. Transistor-level
d. Gate-level
b. Switch-level
c. Transistor-level
d. Gate-level
ANSWER: Gate-level
7. In
the simulation process, which step specifies the conversion of VHDL
intermediate code so that it can be used by the simulator?
a. Compilation
b. Elaboration
c. Initialization
d. Execution
b. Elaboration
c. Initialization
d. Execution
ANSWER: Elaboration
8. Which
among the following is an output generated by synthesis process?
a. Attributes & Library
b. RTL VHDL description
c. Circuit constraints
d. Gate-level net list
b. RTL VHDL description
c. Circuit constraints
d. Gate-level net list
ANSWER: Gate-level net list
9. Register
transfer level description specifies all of the registers in a design &
______ logic between them.
a. Sequential
b. Combinational
c. Both a and b
d. None of the above
b. Combinational
c. Both a and b
d. None of the above
ANSWER: Combinational
10. Which attribute in
synthesis process specify/ies the resistance by controlling the quantity of
current it can source?
a. Load attribute
b. Drive attribute
c. Arrival time attribute
d. All of the above
b. Drive attribute
c. Arrival time attribute
d. All of the above
ANSWER: Drive attribute
11. Which type of digital
systems exhibit the necessity for the existence of at least one feedback path
from output to input?
a. Combinational System
b. Sequential system
c. Both a and b
d. None of the above
b. Sequential system
c. Both a and b
d. None of the above
ANSWER: Sequential system
12. The output of
sequential circuit is regarded as a function of time sequence of __________.
A. Inputs
B. Outputs
C. Internal States
D. External States
A. Inputs
B. Outputs
C. Internal States
D. External States
a. A & D
b. A & C
c. B & D
d. B & C
b. A & C
c. B & D
d. B & C
ANSWER: A & C
13. The time required for
an input data to settle _____ the triggering edge of clock is known as ‘Setup Time’.
a. Before
b. During
c. After
d. All of the above
b. During
c. After
d. All of the above
ANSWER: Before
14. Hold time is defined
as the time required for the data to ________ after the triggering edge of
clock.
a. Increase
b. Decrease
c. Remain stable
d. All of the above
b. Decrease
c. Remain stable
d. All of the above
ANSWER: Remain stable
15. An Antifuse programming
technology is predominantly associated with _____.
a. SPLDs
b. FPGAs
c. CPLDs
d. All of the above
b. FPGAs
c. CPLDs
d. All of the above
ANSWER: FPGAs
Subscribe to:
Post Comments
(
Atom
)
No comments :
Post a Comment